What is the probability of a soft error occurring in a chip?

According to the descriptions in both the AEC-Q100 and IEC 61508 standards, for 1Mbit RAM chip by 130-nanometer-process, the soft error rate (SER) induced by atmospheric neutron single-event effects exceeds 1000 FIT. FIT is defined as one failure occurring in 10⁹ hours of operation. Thus, a device with a failure rate of 100 FIT is expected to operate safely for 10⁷ hours on average. Although this figure may appear large at first glance, it becomes particularly alarming for devices subject to stringent safety requirements, such as those used in automotive braking systems.

Based on the severity of hazards associated with their application scenarios, automotive chips are classified into different safety integrity levels, QM and ASIL-A through ASIL-D. ASIL-D represents the highest level and thus the most stringent safety requirements. The industry determines these safety levels by evaluating three key metrics of a chip, as illustrated in the figure below. It is evident that a failure rate of 1000 FIT significantly exceeds the requirement for ASIL-B. This also implies that, for CMOS designs fabricated using the 130nm process, as the density and capacity of sequential memory elements increase, the demands on functional safety become even more rigorous.

Automotive safety standards impose specific requirements on components, particularly for ASIL-D–rated systems such as powertrain control, braking systems, and Electronic Braking Systems (EBS). The control chips used in these systems are typically required to meet the ASIL-D level. If such chips fail in safety-critical functions, the consequences could be catastrophic. For instance, a braking system could pose immeasurable risks to drivers and passengers, where a "random fault" causes a critical brake command to be missed.

Moreover, soft errors originate from unpredictable sources, compelling designers to implement error-mitigation strategies at every level of the system architecture. With advancing process technologies, most modern chips are now manufactured using 28nm or even 7nm nodes. However, devices built with these advanced nodes exhibit significantly reduced resilience to soft errors and are increasingly susceptible to Multiple-Bit Upset (MBU) faults where multiple bits flip simultaneously, far more challenging to correct.

In fact, devices designed with 28nm CMOS technology demonstrate a soft error rate that is at least three orders of magnitude higher than those fabricated with 130nm technology. This dramatic increase poses a substantially greater challenge to functional safety design in automotive systems.

Since this "thing" can't be avoided, does that mean nobody can use chips anymore?

For commercial or standard industrial-grade components, even if a chip failure occurs, it can typically be resolved simply by rebooting or resetting the system, causing no harm to people or property and thus being of little consequence. However, in applications involving public safety, including automotive systems requiring ASIL-D compliance or industrial systems requiring to meet SIL-1 safety integrity levels, the chip’s susceptibility to such failures must be carefully evaluated and addressed.

It’s worth noting that there are actually quite a few technical approaches available to enhance a device’s resilience against soft errors. In space applications, for instance, components are often designed and manufactured with little regard for cost, as mission success is paramount. However, devices on the ground must not only meet stringent safety requirements but also achieve exceptional cost-effectiveness, which is a far more challenging balancing act.